Schedule
09:00 - 09:10
PMBS Introduction and Welcome
Session 1: Best Papers
09:10 - 09:30
Memory Demands in Disaggregated HPC: How Accurate Do We Need to Be?
Felippe Vieira Zacarias, Paul Carpenter
Barcelona Supercomputing Center (BSC), Spain
Vinicius Petrucci
University of Pittsburgh, PA
Universidade Federal da Bahia, Brazil
09:30 - 10:00
Architectural Requirements for Deep-learning Workloads in HPC Environments
Khaled Ibrahim, Tan Nguyen, Hai Ah Nam, Wahid Bhimji, Steven Farrell, Leonid Oliker, Michael Rowan, Nick Wright, Samuel Williams
Lawrence Berkeley National Laboratory, CA
10:00 - 10:30 Break
Session 2: Modeling and Simulation
10:30 - 11:00
Multilevel simulation-based co-design of next generation HPC microprocessors
Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill
Atomic Energy and Alternative Energies Commission (CEA), France
Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez
Forschungszentrum Jülich, Institute for Advanced Simulation, Germany
Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis
Institute of Computer Science, Foundation for Research and Technology - Hellas, Greece
Milan Radulovic, Francesc Martinez, Adria Armejach, Marc Casas
Barcelona Supercomputing Center (BSC), Spain
Alejandro Nocua
Bull Atos, France
Romain Dolbeau
Sipearl, France
11:00 - 11:30
An Extended Roofline Performance Model with PCI-E and Network Ceilings
Amanda Dufek, Jack Deslippe, Paul Lin, Brandon Cook
Lawrence Berkeley National Laboratory, CA
Charlene Yang
NVIDIA, CA
Jonathan Madsen
Advanced Micro Devices, TX
11:30 - 12:00
Exploration of Congestion Control Techniques on Dragonfly-class HPC Networks Through Simulation
Neil McGlohon, Christopher D. Carothers
Rensselaer Polytechnic Institute (RPI), NY
Scott Hemmert, Michael Levenhagen
Sandia National Laboratories, NM
Kevin A. Brown, Sudheer Chunduri, Robert B. Ross
Argonne National Laboratory, IL
12:00 - 12:30
Understanding power variation and its implications on performance optimization on the Cori supercomputer
Sridutt Bhalachandra, Brian Austin, Nick Wright
Lawrence Berkeley National Laboratory, CA
12:30 - 14:00 Lunch
Session 3: Short Papers
14:00 - 14:20
Using the Semi-Stencil Algorithm to Accelerate High-Order Stencils on GPUs
Ryuichi Sai, John Mellor-Crummey, Xiaozhu Meng
Rice University, TX
Mauricio Araya-Polo, Jie Meng
TotalEnergies E&P Research and Technology, TX
14:20 - 14:40
MicroBench Maker: Reproduce, Reuse, Improve
Sascha Hunold, Jordy Ajanohoun
Vienna University of Technology, Austria
Alexandra Carpen-Amarie
Fraunhofer ITWM, Germany
14:40 - 15:00
Enabling Cache Aware Roofline analysis with Portable Hardware Counter Metrics
Brian Gravelle, William D. Nystrom
Los Alamos National Laboratory, NM
Dewi Yokelson, Boyana Norris
University of Oregon, OR
15:00 - 15:30 Break
Session 4: Performance Portability and Optimization
15:30 - 16:00
Customized Monte Carlo Tree Search for LLVM/Polly’s Composable Loop Optimization Transformations
Jaehoon Koo, Prasanna Balaprakash, Michael Kruse, Xingfu Wu, Paul Hovland
Argonne National Laboratory, IL
Mary Hall
University of Utah, UT
16:00 - 16:30
Comparing Julia to Performance Portable Parallel Programming Models for HPC
Wei-Chen Lin, Simon McIntosh-Smith
University of Bristol, UK
16:30 - 17:00
Bayesian Optimization for auto-tuning GPU kernels
Floris-Jan Q. Willemsen, Rob V. van Nieuwpoort, Ben van Werkhoven
Netherlands eScience Center, University of Amsterdam, Netherlands
17:00 - 17:30
Narrowing the Search Space of Applications Mapping on Hierarchical Topologies
Nicolas Denoyelle, Swann Perarnau, Brice Videau, Pete Beckman,
Argonne National Laboratory, IL
Emmanuel Jeannot
INRIA, France
17:30 - 17:40
PMBS End